A 5.83 pj/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65 nm CMOS

Xiongxin Zhao, Zhixiang Chen, Xiao Peng, Dajiang Zhou, Satoshi Goto

    研究成果: Article

    抜粋

    In this paper, we propose a synthesizable LDPC decoder IP core for the WiMAX system with high parallelism and enhanced error-correcting performance. By taking the advantages of both layered scheduling and fully-parallel architecture, the decoder can fully support multi-mode decoding specified in WiMAX with the parallelism much higher than commonly used partial-parallel layered LDPC decoder architecture. 6-bit quantized messages are split into bit-serial style and 2 bit-width serial processing lines work concurrently so that only 3 cycles are required to decode one layer. As a result, 12~24 cycles are enough to process one iteration for all the code-rates specified in WiMAX. Compared to our previous bit-serial decoder, it doubles the parallelism and solves the message saturation problem of the bit-serial arithmetic, with minor gate count increase. Power synthesis result shows that the proposed decoder achieves 5.83pJ/bit/iteration energy efficiency which is 46.8% improvement compared to state-of-the-art work. Furthermore, an advanced dynamic quantization (ADQ) technique is proposed to enhance the error-correcting performance in layered decoder architecture. With about 2% area overhead, 6-bit ADQ can achieve the error-correcting performance close to 7-bit fixed quantization with improved error floor performance.

    元の言語English
    ページ(範囲)2623-2632
    ページ数10
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E96-A
    発行部数12
    DOI
    出版物ステータスPublished - 2013

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

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