A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

Takeshi Nakayama, Shin ichi Kobayashi, Yoshikazu Miyawaki, Yasushi Terada, Natsuo Ajika, Makoto Ohi, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara, Kimio Suzuki

研究成果: Article

2 引用 (Scopus)

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An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.

元の言語English
ページ(範囲)1600-1605
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
26
発行部数11
DOI
出版物ステータスPublished - 1991 11
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Nakayama, T., Kobayashi, S. I., Miyawaki, Y., Terada, Y., Ajika, N., Ohi, M., Arima, H., Matsukawa, T., Yoshihara, T., & Suzuki, K. (1991). A 60-ns 16-Mb flash EEPROM with program and erase sequence controller. IEEE Journal of Solid-State Circuits, 26(11), 1600-1605. https://doi.org/10.1109/4.98978