A 60-ns 4-Mbit CMOS DRAM with Built-In Self-Test Function

Takashi Ohsawa, Tohru Furuyama, Yohji Watanabe, Hiroto Tanaka, Kenji Natori, Satoshi Shinozaki, Takeshi Tanaka, Satoshi Yamano, Yohsei Nagahama, Natsuki Kushiyama, Kenji Tsuchida

研究成果: Article

16 被引用数 (Scopus)

抄録

A 4-Mbit CMOS DRAM measuring 6.9×16.11 mm2 has been fabricated using a 0.9-µm twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5 × 5.5 µm2 each, are incorporated in a p-well. A novel built-in self-test (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mbit CMOS DRAM with 60-ns access time, 50-mA active current, and 200-µA standby current is realized by widening the DQ line bus which connects the sense amplifiers with the DQ buffers, thereby reducing the parasitic capacitance of the DQ lines.

本文言語English
ページ(範囲)663-668
ページ数6
ジャーナルIEEE Journal of Solid-State Circuits
22
5
DOI
出版ステータスPublished - 1987 10
外部発表はい

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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