A 64-bit carry look ahead adder using pass transistor BiCMOS gates

Kimio Ueda*, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko

*この研究の対応する著者

研究成果: Article査読

10 被引用数 (Scopus)

抄録

This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this gate has a rail-to-rail output voltage. Therefore the next gate does not have a large degradation of its driving capability. The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance. The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits. In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 μm BiCMOS process with single-polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology. Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder.

本文言語English
ページ(範囲)810-817
ページ数8
ジャーナルIEEE Journal of Solid-State Circuits
31
6
DOI
出版ステータスPublished - 1996 6
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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