A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits

S. Ohbayashi, M. Yabuuchi, K. Nii, Y. Tsukamoto, S. Imaoka, Y. Oda, M. Igarashi, M. Takeuchi, H. Kawashima, H. Makino, Y. Yamaguchi, K. Tsukamoto, M. Inuishi, K. Ishibashi, H. Shinohara

研究成果: Conference contribution

41 引用 (Scopus)

抜粋

We propose a new design scheme to improve the SRAM read and write operation margins in the presence of a large Vth variability. By applying this scheme to a 0.494 μm2 SRAM cell with a β ratio of 1, which is an aggressively small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth value using a 65 nm LSTP CMOS technology.

元の言語English
ホスト出版物のタイトル2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
ページ17-18
ページ数2
出版物ステータスPublished - 2006 12 1
イベント2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
継続期間: 2006 6 152006 6 17

出版物シリーズ

名前IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2006 Symposium on VLSI Circuits, VLSIC
United States
Honolulu, HI
期間06/6/1506/6/17

    フィンガープリント

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

これを引用

Ohbayashi, S., Yabuuchi, M., Nii, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Igarashi, M., Takeuchi, M., Kawashima, H., Makino, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Ishibashi, K., & Shinohara, H. (2006). A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits. : 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 17-18). [1705290] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).