A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Shigeki Ohbayashi*, Makoto Yabuuchi, Koji Nil, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

*この研究の対応する著者

研究成果: Article査読

93 被引用数 (Scopus)

抄録

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

本文言語English
ページ(範囲)820-829
ページ数10
ジャーナルIEEE Journal of Solid-State Circuits
42
4
DOI
出版ステータスPublished - 2007 4
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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