A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nil, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

研究成果: Article

86 引用 (Scopus)

抜粋

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

元の言語English
ページ(範囲)820-829
ページ数10
ジャーナルIEEE Journal of Solid-State Circuits
42
発行部数4
DOI
出版物ステータスPublished - 2007 4 1
外部発表Yes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Ohbayashi, S., Yabuuchi, M., Nil, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Yoshihara, T., Igarashi, M., Takeuchi, M., Kawashima, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Makino, H., Ishibashi, K., & Shinohara, H. (2007). A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits. IEEE Journal of Solid-State Circuits, 42(4), 820-829. https://doi.org/10.1109/JSSC.2007.891648