A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

Shigeki Ohbayashi*, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Qkada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

*この研究の対応する著者

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

本文言語English
ホスト出版物のタイトル2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
ページ488-489+617+485
DOI
出版ステータスPublished - 2007 9 27
外部発表はい
イベント54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
継続期間: 2007 2 112007 2 15

出版物シリーズ

名前Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN(印刷版)0193-6530

Other

Other54th IEEE International Solid-State Circuits Conference, ISSCC 2007
国/地域United States
CitySan Francisco, CA
Period07/2/1107/2/15

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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