A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

Takeshi Hamamoto, Kiyohiro Furutani, Takashi Kubo, Satoshi Kawasaki, Hironori Iga, Takashi Kono, Yasuhiro Konishi, Tsutomu Yoshihara

研究成果: Article

30 引用 (Scopus)

抜粋

This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-μm DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.

元の言語English
ページ(範囲)194-206
ページ数13
ジャーナルIEEE Journal of Solid-State Circuits
39
発行部数1
DOI
出版物ステータスPublished - 2004 1
外部発表Yes

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

これを引用

Hamamoto, T., Furutani, K., Kubo, T., Kawasaki, S., Iga, H., Kono, T., Konishi, Y., & Yoshihara, T. (2004). A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. IEEE Journal of Solid-State Circuits, 39(1), 194-206. https://doi.org/10.1109/JSSC.2003.820851