In this paper, we introduce an LDPC decoder design for decoding length-672 code adopted in IEEE 802.15.3c standard. The proposed decoder features high performance in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. The decoder takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because of the more complicated interconnection network used for message passing. This problem is nicely solved by our proposed efficient message permutation scheme utilizing the parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30mm 2 with area utilization ratio 86.3%. According to the measurement results, working at 1.2V, 400 MHz and 10 iterations the proposed decoder delivers a 6.72Gb/s data throughput and dissipates a power of 537.6mW, resulting in an energy efficiency 8.0pJ/bit/iteration.
|ホスト出版物のタイトル||2011 International Symposium on Integrated Circuits, ISIC 2011|
|出版ステータス||Published - 2011|
|イベント||2011 International Symposium on Integrated Circuits, ISIC 2011 - SingaporeSingapore|
継続期間: 2011 12 12 → 2011 12 14
|Other||2011 International Symposium on Integrated Circuits, ISIC 2011|
|Period||11/12/12 → 11/12/14|
ASJC Scopus subject areas