A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.

    本文言語English
    ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    ページ87-88
    ページ数2
    DOI
    出版ステータスPublished - 2013
    イベント2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama
    継続期間: 2013 1 222013 1 25

    Other

    Other2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
    CityYokohama
    Period13/1/2213/1/25

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

    フィンガープリント 「A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

    引用スタイル