A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto

    研究成果: Conference contribution

    1 引用 (Scopus)

    抜粋

    An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.

    元の言語English
    ホスト出版物のタイトルProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
    ページ87-88
    ページ数2
    DOI
    出版物ステータスPublished - 2013
    イベント2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama
    継続期間: 2013 1 222013 1 25

    Other

    Other2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
    Yokohama
    期間13/1/2213/1/25

      フィンガープリント

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Science Applications
    • Computer Graphics and Computer-Aided Design

    これを引用

    Chen, Z., Peng, X., Zhao, X., Okamura, L., Zhou, D., & Goto, S. (2013). A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. : Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 87-88). [6509569] https://doi.org/10.1109/ASPDAC.2013.6509569