A 7-round parallel hardware-saving accelerator for Gaussian and DoG pyramid construction part of SIFT

Jingbang Qiu, Tianci Huang, Takeshi Ikenaga

研究成果: Conference contribution

7 引用 (Scopus)

抄録

SIFT, short for Scale Invariant Feature Transform, is regarded as one of the most robust feature detection algorithms. The Gaussian and DoG Pyramid Construction part, functioning as computation basis and searching spaces for other parts, proves fatal to the system. In this paper, we present an FPGA-implementable hardware accelerator for this part. Stratified Gaussian Convolution scheme and 7-Round Parallel Computation scheme are introduced to reduce the hardware cost and improve process speed, meanwhile keeping high accuracy. In our experiment, our proposal successfully realizes a system with max clock frequency of 95.0 MHz, and on-system process speed of up to 21 fps for VGA format images. Hardware cost of Slice LUTs is reduced by 12.1% compared with traditional work. Accuracy is kept as high as 98.27% against original software solution. Our proposed structure proves to be suitable for real-time SIFT systems.

元の言語English
ホスト出版物のタイトルLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
ページ75-84
ページ数10
5996 LNCS
エディションPART 3
DOI
出版物ステータスPublished - 2010
イベント9th Asian Conference on Computer Vision, ACCV 2009 - Xi'an
継続期間: 2009 9 232009 9 27

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
番号PART 3
5996 LNCS
ISSN(印刷物)03029743
ISSN(電子版)16113349

Other

Other9th Asian Conference on Computer Vision, ACCV 2009
Xi'an
期間09/9/2309/9/27

Fingerprint

Scale Invariant Feature Transform
Pyramid
Accelerator
Particle accelerators
Hardware
Hardware Accelerator
Real time systems
Convolution
Feature Detection
Field programmable gate arrays (FPGA)
Costs
Clocks
Parallel Computation
Mathematical transformations
Slice
Field Programmable Gate Array
High Accuracy
Real-time
Software
Experiments

ASJC Scopus subject areas

  • Computer Science(all)
  • Theoretical Computer Science

これを引用

Qiu, J., Huang, T., & Ikenaga, T. (2010). A 7-round parallel hardware-saving accelerator for Gaussian and DoG pyramid construction part of SIFT. : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) (PART 3 版, 巻 5996 LNCS, pp. 75-84). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 巻数 5996 LNCS, 番号 PART 3). https://doi.org/10.1007/978-3-642-12297-2_8

A 7-round parallel hardware-saving accelerator for Gaussian and DoG pyramid construction part of SIFT. / Qiu, Jingbang; Huang, Tianci; Ikenaga, Takeshi.

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 巻 5996 LNCS PART 3. 編 2010. p. 75-84 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); 巻 5996 LNCS, 番号 PART 3).

研究成果: Conference contribution

Qiu, J, Huang, T & Ikenaga, T 2010, A 7-round parallel hardware-saving accelerator for Gaussian and DoG pyramid construction part of SIFT. : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). PART 3 Edn, 巻. 5996 LNCS, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 番号 PART 3, 巻. 5996 LNCS, pp. 75-84, 9th Asian Conference on Computer Vision, ACCV 2009, Xi'an, 09/9/23. https://doi.org/10.1007/978-3-642-12297-2_8
Qiu J, Huang T, Ikenaga T. A 7-round parallel hardware-saving accelerator for Gaussian and DoG pyramid construction part of SIFT. : Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). PART 3 版 巻 5996 LNCS. 2010. p. 75-84. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); PART 3). https://doi.org/10.1007/978-3-642-12297-2_8
Qiu, Jingbang ; Huang, Tianci ; Ikenaga, Takeshi. / A 7-round parallel hardware-saving accelerator for Gaussian and DoG pyramid construction part of SIFT. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 巻 5996 LNCS PART 3. 版 2010. pp. 75-84 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); PART 3).
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