A 98 GMACs/W 32-core vector processor in 65 nm CMOS

Xun He*, Xin Jin, Minghui Wang, Dajiang Zhou, Satoshi Goto

*この研究の対応する著者

    研究成果: Article査読

    6 被引用数 (Scopus)

    抄録

    This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16 bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192 GB/s low latency inter-core BWin average. The 4-ports L2 cache architecture is also designed to provide 192GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25mm 2 in 65 nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2V.

    本文言語English
    ページ(範囲)2609-2618
    ページ数10
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E94-A
    12
    DOI
    出版ステータスPublished - 2011 12

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • コンピュータ グラフィックスおよびコンピュータ支援設計
    • 応用数学
    • 信号処理

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