A 98 GMACs/W 32-core vector processor in 65nm CMOS

Xun He, Dajiang Zhou, Xin Jin, Satoshi Goto

    研究成果: Conference contribution

    抜粋

    This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.

    元の言語English
    ホスト出版物のタイトルProceedings of the International Symposium on Low Power Electronics and Design
    ページ373-378
    ページ数6
    DOI
    出版物ステータスPublished - 2011
    イベント17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka
    継続期間: 2011 8 12011 8 3

    Other

    Other17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
    Fukuoka
    期間11/8/111/8/3

      フィンガープリント

    ASJC Scopus subject areas

    • Engineering(all)

    これを引用

    He, X., Zhou, D., Jin, X., & Goto, S. (2011). A 98 GMACs/W 32-core vector processor in 65nm CMOS. : Proceedings of the International Symposium on Low Power Electronics and Design (pp. 373-378). [5993669] https://doi.org/10.1109/ISLPED.2011.5993669