This paper presents a fractional motion estimation (FME) design in high efficiency video coding (HEVC) for ultrahigh definition video (Ultra-HD). To reduce complexity and achieve high throughput, the design is co-optimized in algorithm and hardware architecture. Bilinear quarter pixel approximation, together with a 5T12S search pattern is proposed to reduce the complexity of the interpolation and search process. Furthermore, we introduce an exhaustive size-hadamard transform (ES-HAD), to improve coding quality, and determine the best transform size rather than using complex transform coding. Besides, a data reuse method of ES-HAD is applied to reduce the hardware overhead. This design is implemented in 65nm CMOS chip and verified by FPGA based evaluation system. It achieves 995Mpixels/s for 7680×4320 30fps encoding, at least 4.7 times faster than previous designs. Its power dissipation is 198.6mW at 188MHz, with 0.2nJ/pixel power efficiency. Despite high complexity in HEVC, the chip achieves 56% improvement on power efficiency than previous works in H.264.
|ホスト出版物のタイトル||Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013|
|出版ステータス||Published - 2013|
|イベント||2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 - Singapore|
継続期間: 2013 11 11 → 2013 11 13
|Other||2013 9th IEEE Asian Solid-State Circuits Conference, A-SSCC 2013|
|Period||13/11/11 → 13/11/13|
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