A bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding

Jinjia Zhou*, Dajiang Zhou, Gang He, Satoshi Goto

*この研究の対応する著者

研究成果: Conference contribution

抄録

In this paper, a bandwidth reduction scheme and its VLSI implementation for H.264/AVC motion vector decoding component is proposed to save the DRAM traffic. In this component, the motion information including motion vector and reference index, for the co-located picture and the last decoded line, is stored in DRAM. In order to save the DRAM access, a partition based storage format is first applied to condense the MB level data. Then, a DPCM-based variable length coding method is utilized to reduce the data size of each partition. Finally, the total bandwidth is further reduced by combining the co-located and last-line information. Experimental results show that the bandwidth requirement for motion vector calculation can be reduced by 85%~98% on typical 1080p and QFHD sequences, with only 7.8k additional logic gates. This can contribute to near 20% bandwidth reduction for the whole video decoder system.

本文言語English
ホスト出版物のタイトルLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
ページ52-61
ページ数10
6298 LNCS
PART 2
DOI
出版ステータスPublished - 2010
イベント11th Pacific Rim Conference on Multimedia, PCM 2010 - Shanghai
継続期間: 2010 9 212010 9 24

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
番号PART 2
6298 LNCS
ISSN(印刷版)03029743
ISSN(電子版)16113349

Other

Other11th Pacific Rim Conference on Multimedia, PCM 2010
CityShanghai
Period10/9/2110/9/24

ASJC Scopus subject areas

  • コンピュータ サイエンス(全般)
  • 理論的コンピュータサイエンス

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