A behavior-based reconfigurable cache for the low-power embedded processor

Jiongyao Ye, Jiannan Jin, Tabkahiro Watanabe

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In embedded processor designs, a cache becomes the main contributor of the power consumption as it greatly improves the performance. The conventional low-power techniques of a cache based on a fixed hardware configuration cannot be configured and it is independent on the program behavior. Thus, a configurable cache is proposed to save energy and improve performance by dynamically adjusting the cache parameters for the code that is executing. However, most existing configurable caches explore and adapt the optimal configuration based on successive time-intervals, which presents efficiency only if the program can keep its execution phase for a number of intervals. In this paper, we propose a behavior-based configurable cache, which can be dynamically adjusted based on the program behavior. The design adds very little hardware complexity and commits most workload to the software, so that it is very effective for the embedded microprocessors design. Simulation by using Spec 2000 shows that our proposed configurable cache can reduce the power consumption by up to 60.6% and 22.3% compared to a conventional set-associative cache and a temporal-based configurable cache, respectively. At the same time, performance degradation is about 0.75%.

本文言語English
ホスト出版物のタイトルProceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
ページ1-5
ページ数5
DOI
出版ステータスPublished - 2011 12 1
イベント2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China
継続期間: 2011 10 252011 10 28

出版物シリーズ

名前Proceedings of International Conference on ASIC
ISSN(印刷版)2162-7541
ISSN(電子版)2162-755X

Conference

Conference2011 IEEE 9th International Conference on ASIC, ASICON 2011
CountryChina
CityXiamen
Period11/10/2511/10/28

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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