A behavior-based reconfigurable cache for the low-power embedded processor

Jiongyao Ye, Jiannan Jin, Takahiro Watanabe

研究成果: Conference contribution

1 引用 (Scopus)

抄録

In embedded processor designs, a cache becomes the main contributor of the power consumption as it greatly improves the performance. The conventional low-power techniques of a cache based on a fixed hardware configuration cannot be configured and it is independent on the program behavior. Thus, a configurable cache is proposed to save energy and improve performance by dynamically adjusting the cache parameters for the code that is executing. However, most existing configurable caches explore and adapt the optimal configuration based on successive time-intervals, which presents efficiency only if the program can keep its execution phase for a number of intervals. In this paper, we propose a behavior-based configurable cache, which can be dynamically adjusted based on the program behavior. The design adds very little hardware complexity and commits most workload to the software, so that it is very effective for the embedded microprocessors design. Simulation by using Spec 2000 shows that our proposed configurable cache can reduce the power consumption by up to 60.6% and 22.3% compared to a conventional set-associative cache and a temporal-based configurable cache, respectively. At the same time, performance degradation is about 0.75%.

元の言語English
ホスト出版物のタイトルProceedings of International Conference on ASIC
ページ1-5
ページ数5
DOI
出版物ステータスPublished - 2011
イベント2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen
継続期間: 2011 10 252011 10 28

Other

Other2011 IEEE 9th International Conference on ASIC, ASICON 2011
Xiamen
期間11/10/2511/10/28

Fingerprint

Electric power utilization
Hardware
Microprocessor chips
Degradation

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

これを引用

Ye, J., Jin, J., & Watanabe, T. (2011). A behavior-based reconfigurable cache for the low-power embedded processor. : Proceedings of International Conference on ASIC (pp. 1-5). [6157107] https://doi.org/10.1109/ASICON.2011.6157107

A behavior-based reconfigurable cache for the low-power embedded processor. / Ye, Jiongyao; Jin, Jiannan; Watanabe, Takahiro.

Proceedings of International Conference on ASIC. 2011. p. 1-5 6157107.

研究成果: Conference contribution

Ye, J, Jin, J & Watanabe, T 2011, A behavior-based reconfigurable cache for the low-power embedded processor. : Proceedings of International Conference on ASIC., 6157107, pp. 1-5, 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, 11/10/25. https://doi.org/10.1109/ASICON.2011.6157107
Ye J, Jin J, Watanabe T. A behavior-based reconfigurable cache for the low-power embedded processor. : Proceedings of International Conference on ASIC. 2011. p. 1-5. 6157107 https://doi.org/10.1109/ASICON.2011.6157107
Ye, Jiongyao ; Jin, Jiannan ; Watanabe, Takahiro. / A behavior-based reconfigurable cache for the low-power embedded processor. Proceedings of International Conference on ASIC. 2011. pp. 1-5
@inproceedings{0e48b97f9d99463e8b9060a7cb835928,
title = "A behavior-based reconfigurable cache for the low-power embedded processor",
abstract = "In embedded processor designs, a cache becomes the main contributor of the power consumption as it greatly improves the performance. The conventional low-power techniques of a cache based on a fixed hardware configuration cannot be configured and it is independent on the program behavior. Thus, a configurable cache is proposed to save energy and improve performance by dynamically adjusting the cache parameters for the code that is executing. However, most existing configurable caches explore and adapt the optimal configuration based on successive time-intervals, which presents efficiency only if the program can keep its execution phase for a number of intervals. In this paper, we propose a behavior-based configurable cache, which can be dynamically adjusted based on the program behavior. The design adds very little hardware complexity and commits most workload to the software, so that it is very effective for the embedded microprocessors design. Simulation by using Spec 2000 shows that our proposed configurable cache can reduce the power consumption by up to 60.6{\%} and 22.3{\%} compared to a conventional set-associative cache and a temporal-based configurable cache, respectively. At the same time, performance degradation is about 0.75{\%}.",
author = "Jiongyao Ye and Jiannan Jin and Takahiro Watanabe",
year = "2011",
doi = "10.1109/ASICON.2011.6157107",
language = "English",
isbn = "9781612841908",
pages = "1--5",
booktitle = "Proceedings of International Conference on ASIC",

}

TY - GEN

T1 - A behavior-based reconfigurable cache for the low-power embedded processor

AU - Ye, Jiongyao

AU - Jin, Jiannan

AU - Watanabe, Takahiro

PY - 2011

Y1 - 2011

N2 - In embedded processor designs, a cache becomes the main contributor of the power consumption as it greatly improves the performance. The conventional low-power techniques of a cache based on a fixed hardware configuration cannot be configured and it is independent on the program behavior. Thus, a configurable cache is proposed to save energy and improve performance by dynamically adjusting the cache parameters for the code that is executing. However, most existing configurable caches explore and adapt the optimal configuration based on successive time-intervals, which presents efficiency only if the program can keep its execution phase for a number of intervals. In this paper, we propose a behavior-based configurable cache, which can be dynamically adjusted based on the program behavior. The design adds very little hardware complexity and commits most workload to the software, so that it is very effective for the embedded microprocessors design. Simulation by using Spec 2000 shows that our proposed configurable cache can reduce the power consumption by up to 60.6% and 22.3% compared to a conventional set-associative cache and a temporal-based configurable cache, respectively. At the same time, performance degradation is about 0.75%.

AB - In embedded processor designs, a cache becomes the main contributor of the power consumption as it greatly improves the performance. The conventional low-power techniques of a cache based on a fixed hardware configuration cannot be configured and it is independent on the program behavior. Thus, a configurable cache is proposed to save energy and improve performance by dynamically adjusting the cache parameters for the code that is executing. However, most existing configurable caches explore and adapt the optimal configuration based on successive time-intervals, which presents efficiency only if the program can keep its execution phase for a number of intervals. In this paper, we propose a behavior-based configurable cache, which can be dynamically adjusted based on the program behavior. The design adds very little hardware complexity and commits most workload to the software, so that it is very effective for the embedded microprocessors design. Simulation by using Spec 2000 shows that our proposed configurable cache can reduce the power consumption by up to 60.6% and 22.3% compared to a conventional set-associative cache and a temporal-based configurable cache, respectively. At the same time, performance degradation is about 0.75%.

UR - http://www.scopus.com/inward/record.url?scp=84860864885&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84860864885&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2011.6157107

DO - 10.1109/ASICON.2011.6157107

M3 - Conference contribution

AN - SCOPUS:84860864885

SN - 9781612841908

SP - 1

EP - 5

BT - Proceedings of International Conference on ASIC

ER -