A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing

研究成果: Conference contribution

抄録

A high-speed FIR filter structure is proposed in this paper by utilizing bit-segmentation adders and symmetric transpose 2-block FIR structure. First, a bit-segmented adder chain-based design is proposed with bit-segmentation adders. Second, a basic unit design of symmetric transpose block FIR is proposed to reduce the critical path delay. The evaluation results show that, when compared with state-of-the-art high-speed CSD multiplier-based FIR filter design, the proposed design requires 14.1% less area while provides 7.9% frequency improvement, 10.2% reduction of power consumption, 22.8% reduction of energy-delay-product and 20.4% reduction of area-delay-product, which shows the effectiveness of the proposed method.

本文言語English
ホスト出版物のタイトルProceedings - APCCAS 2019
ホスト出版物のサブタイトル2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption
出版社Institute of Electrical and Electronics Engineers Inc.
ページ29-32
ページ数4
ISBN(電子版)9781728129402
DOI
出版ステータスPublished - 2019 11
イベント15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019 - Bangkok, Thailand
継続期間: 2019 11 112019 11 14

出版物シリーズ

名前Proceedings - APCCAS 2019: 2019 IEEE Asia Pacific Conference on Circuits and Systems: Innovative CAS Towards Sustainable Energy and Technology Disruption

Conference

Conference15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019
CountryThailand
CityBangkok
Period19/11/1119/11/14

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Renewable Energy, Sustainability and the Environment
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Instrumentation

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