A bit-write reduction method based on error-correcting codes for non-volatile memories

研究成果: Conference contribution

5 被引用数 (Scopus)

抄録

Non-volatile memory has many advantages over SRAM. However, one of its largest problems is that it consumes a large amount of energy in writing. In this paper, we propose a bit-write reduction method based on error correcting codes for non-volatile memories. When a data is written into a memory cell, we do not write it directly but encode it into a codeword. We focus on error-correcting codes and generate new codes called write-reduction codes. In our write-reduction codes, each data corresponds to an information vector in an error-correcting code and an information vector corresponds not to a single codeword but a set of write-reduction codewords. Given a writing data and current memory bits, we can deterministically select a particular write-reduction codeword corresponding to a data to be written, where the maximum number of flipped bits are theoretically minimized. Then the number of writing bits into memory cells will also be minimized. We perform several experimental evaluations and demonstrate up to 72% energy reduction.

本文言語English
ホスト出版物のタイトル20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
出版社Institute of Electrical and Electronics Engineers Inc.
ページ496-501
ページ数6
ISBN(印刷版)9781479977925
DOI
出版ステータスPublished - 2015 3 11
イベント2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan
継続期間: 2015 1 192015 1 22

Other

Other2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
CountryJapan
CityChiba
Period15/1/1915/1/22

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Control and Systems Engineering
  • Modelling and Simulation

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