A built‐in self‐test structure for arithmetic execution units of VLSIs

Takeshi Ikenaga, Jun‐Ichi ‐I Takahashi

研究成果: Article

抄録

This paper proposes advanced built‐in self‐test (BIST) structures: a bit‐distributed pattern generator (BDPG) and a multistage space compressor (MSSC) for arithmetic execution units of VLSIs. By focusing on the regularity of the arithmetic execution units, the required area overhead of the BIST circuits is less than that of conventional ones. The experimental result shows that these structures can reduce almost 60 percent of the hardware overhead of conventional BIST circuits while maintaining high‐fault coverage. These BIST configurations will make a significant contribution to test cost reduction for the performance‐orientation digital LSIs, especially digital signal processor LSIs.

本文言語English
ページ(範囲)68-78
ページ数11
ジャーナルElectronics and Communications in Japan (Part II: Electronics)
78
4
DOI
出版ステータスPublished - 1995 4
外部発表はい

ASJC Scopus subject areas

  • Physics and Astronomy(all)
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

フィンガープリント 「A built‐in self‐test structure for arithmetic execution units of VLSIs」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル