This paper proposes advanced built‐in self‐test (BIST) structures: a bit‐distributed pattern generator (BDPG) and a multistage space compressor (MSSC) for arithmetic execution units of VLSIs. By focusing on the regularity of the arithmetic execution units, the required area overhead of the BIST circuits is less than that of conventional ones. The experimental result shows that these structures can reduce almost 60 percent of the hardware overhead of conventional BIST circuits while maintaining high‐fault coverage. These BIST configurations will make a significant contribution to test cost reduction for the performance‐orientation digital LSIs, especially digital signal processor LSIs.
|ジャーナル||Electronics and Communications in Japan (Part II: Electronics)|
|出版ステータス||Published - 1995 4|
ASJC Scopus subject areas
- Physics and Astronomy(all)
- Computer Networks and Communications
- Electrical and Electronic Engineering