An all PMOS charge pump circuit without over-stress is proposed in low-voltage standard process in this paper. The proposed circuit can reduce the equivalent on-resistancc of the charge-transfer transistors and can avoid the body effect due to the two pumping branches architecture. Therefore, its voltage pumping efficiency is much higher than that of the conventional designs. Moreover, the maximum gate-source, gate-drain and drain-source voltages of all transistors in the proposed charge pump circuit do not exceed the power supply voltage Vdd. The proposed charge pump circuit has been realized in a standard CMOS N-Well 0.35 μm technology. The measured results demonstrate that the proposed charge pump circuit has very high voltage pumping efficiency without overstress. Therefore, the proposed circuit is suitable for implementation in low-voltage CMOS standard process.
|ホスト出版物のタイトル||IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007|
|出版ステータス||Published - 2007|
|イベント||IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan|
継続期間: 2007 12月 20 → 2007 12月 22
|Other||IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007|
|Period||07/12/20 → 07/12/22|
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