A charge pump circuit without overstress in low-voltage CMOS standard process

Jun Pan, Tsutomu Yoshihara

    研究成果: Conference contribution

    14 被引用数 (Scopus)

    抄録

    An all PMOS charge pump circuit without over-stress is proposed in low-voltage standard process in this paper. The proposed circuit can reduce the equivalent on-resistancc of the charge-transfer transistors and can avoid the body effect due to the two pumping branches architecture. Therefore, its voltage pumping efficiency is much higher than that of the conventional designs. Moreover, the maximum gate-source, gate-drain and drain-source voltages of all transistors in the proposed charge pump circuit do not exceed the power supply voltage Vdd. The proposed charge pump circuit has been realized in a standard CMOS N-Well 0.35 μm technology. The measured results demonstrate that the proposed charge pump circuit has very high voltage pumping efficiency without overstress. Therefore, the proposed circuit is suitable for implementation in low-voltage CMOS standard process.

    本文言語English
    ホスト出版物のタイトルIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
    ページ501-504
    ページ数4
    DOI
    出版ステータスPublished - 2007
    イベントIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan
    継続期間: 2007 12 202007 12 22

    Other

    OtherIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
    CityTainan
    Period07/12/2007/12/22

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

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