A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

Hiroshi Fuketa*, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

*この研究の対応する著者

研究成果: Conference contribution

21 被引用数 (Scopus)

抄録

In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

本文言語English
ホスト出版物のタイトル2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
出版社Institute of Electrical and Electronics Engineers Inc.
ページ984-989
ページ数6
ISBN(印刷版)9781450306362
DOI
出版ステータスPublished - 2011 1月 1
外部発表はい

出版物シリーズ

名前Proceedings - Design Automation Conference
ISSN(印刷版)0738-100X

ASJC Scopus subject areas

  • コンピュータ サイエンスの応用
  • 制御およびシステム工学
  • 電子工学および電気工学
  • モデリングとシミュレーション

フィンガープリント

「A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル