抄録
A low power CMOS voltage reference using body effect and switched-capacitor technique is presented in this paper. The output voltage is produced by the gate-source voltage. The MOSFETs are working on subthreshold region thus the power consumption is greatly reduced. By utilizing the switched-capacitor technique, only one transistor is required to generate the reference voltage, so that the threshold voltage mismatch in conventional two-transistor configuration is eliminated. The proposed circuit is designed and simulated under 0.18-μm CMOS technology. The output voltage is 117.68 mV, and the temperature coefficient is less than 50.0 ppm/°C ranging from -40 °C to 80 °C. The voltage line-sensitivity is 0.19 %/V ranging from 1.2 V to 3.2 V. The average current consumption is about 95 nA.
本文言語 | English |
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ホスト出版物のタイトル | ISOCC 2013 - 2013 International SoC Design Conference |
出版社 | IEEE Computer Society |
ページ | 91-94 |
ページ数 | 4 |
ISBN(印刷版) | 9781479911417 |
DOI | |
出版ステータス | Published - 2013 |
イベント | 2013 International SoC Design Conference, ISOCC 2013 - Busan 継続期間: 2013 11月 17 → 2013 11月 19 |
Other
Other | 2013 International SoC Design Conference, ISOCC 2013 |
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City | Busan |
Period | 13/11/17 → 13/11/19 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学