A precise CMOS voltage reference using body effect and switched-current technique is presented in this paper. To reduce static current, the threshold voltage with body effect in nMOSFET transistor is utilized instead of the V BE of BJT transistor. Owning to the switched-current technique, only one transistor is required to generate the reference voltage, so that the threshold voltage mismatch in conventional two-transistor configuration is eliminated. The proposed circuit is designed and simulated under 0.18-μm CMOS technology. The output voltage is 147.44 mV, and the temperature coefficient is less than 5.2 ppm/°C ranging from -20 °C to 100 °C. The voltage line-sensitivity is 0.44 %/V ranging from 1.5 V to 3.3 V. The power-supply-rejection-ratio (PSRR) is -56 dB at 100 Hz. The average current consumption is about 16 μA.
|ホスト出版物のタイトル||ISOCC 2012 - 2012 International SoC Design Conference|
|出版ステータス||Published - 2012|
|イベント||2012 International SoC Design Conference, ISOCC 2012 - Jeju Island|
継続期間: 2012 11 4 → 2012 11 7
|Other||2012 International SoC Design Conference, ISOCC 2012|
|Period||12/11/4 → 12/11/7|
ASJC Scopus subject areas