抄録
A precise CMOS voltage reference using body effect and switched-current technique is presented in this paper. To reduce static current, the threshold voltage with body effect in nMOSFET transistor is utilized instead of the V BE of BJT transistor. Owning to the switched-current technique, only one transistor is required to generate the reference voltage, so that the threshold voltage mismatch in conventional two-transistor configuration is eliminated. The proposed circuit is designed and simulated under 0.18-μm CMOS technology. The output voltage is 147.44 mV, and the temperature coefficient is less than 5.2 ppm/°C ranging from -20 °C to 100 °C. The voltage line-sensitivity is 0.44 %/V ranging from 1.5 V to 3.3 V. The power-supply-rejection-ratio (PSRR) is -56 dB at 100 Hz. The average current consumption is about 16 μA.
| 元の言語 | English |
|---|---|
| ホスト出版物のタイトル | ISOCC 2012 - 2012 International SoC Design Conference |
| ページ | 92-95 |
| ページ数 | 4 |
| DOI | |
| 出版物ステータス | Published - 2012 |
| イベント | 2012 International SoC Design Conference, ISOCC 2012 - Jeju Island 継続期間: 2012 11 4 → 2012 11 7 |
Other
| Other | 2012 International SoC Design Conference, ISOCC 2012 |
|---|---|
| 市 | Jeju Island |
| 期間 | 12/11/4 → 12/11/7 |
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ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
これを引用
A CMOS voltage reference combining body effect with switched-current technique. / Ren, Ning; Zhang, Hao; Yoshihara, Tsutomu.
ISOCC 2012 - 2012 International SoC Design Conference. 2012. p. 92-95 6407047.研究成果: Conference contribution
}
TY - GEN
T1 - A CMOS voltage reference combining body effect with switched-current technique
AU - Ren, Ning
AU - Zhang, Hao
AU - Yoshihara, Tsutomu
PY - 2012
Y1 - 2012
N2 - A precise CMOS voltage reference using body effect and switched-current technique is presented in this paper. To reduce static current, the threshold voltage with body effect in nMOSFET transistor is utilized instead of the V BE of BJT transistor. Owning to the switched-current technique, only one transistor is required to generate the reference voltage, so that the threshold voltage mismatch in conventional two-transistor configuration is eliminated. The proposed circuit is designed and simulated under 0.18-μm CMOS technology. The output voltage is 147.44 mV, and the temperature coefficient is less than 5.2 ppm/°C ranging from -20 °C to 100 °C. The voltage line-sensitivity is 0.44 %/V ranging from 1.5 V to 3.3 V. The power-supply-rejection-ratio (PSRR) is -56 dB at 100 Hz. The average current consumption is about 16 μA.
AB - A precise CMOS voltage reference using body effect and switched-current technique is presented in this paper. To reduce static current, the threshold voltage with body effect in nMOSFET transistor is utilized instead of the V BE of BJT transistor. Owning to the switched-current technique, only one transistor is required to generate the reference voltage, so that the threshold voltage mismatch in conventional two-transistor configuration is eliminated. The proposed circuit is designed and simulated under 0.18-μm CMOS technology. The output voltage is 147.44 mV, and the temperature coefficient is less than 5.2 ppm/°C ranging from -20 °C to 100 °C. The voltage line-sensitivity is 0.44 %/V ranging from 1.5 V to 3.3 V. The power-supply-rejection-ratio (PSRR) is -56 dB at 100 Hz. The average current consumption is about 16 μA.
KW - body effect
KW - CMOS voltage reference
KW - subthreshold
KW - switched-current technique
UR - http://www.scopus.com/inward/record.url?scp=84873980203&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84873980203&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2012.6407047
DO - 10.1109/ISOCC.2012.6407047
M3 - Conference contribution
AN - SCOPUS:84873980203
SN - 9781467329880
SP - 92
EP - 95
BT - ISOCC 2012 - 2012 International SoC Design Conference
ER -