A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm

Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto

研究成果: Conference contribution

抜粋

A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.

元の言語English
ホスト出版物のタイトルProceedings of the Working Conference on Advanced Visual Interfaces, AVI' 10
ページ207-212
ページ数6
DOI
出版物ステータスPublished - 2010 10 21
イベントInternational Conference on Advanced Visual Interfaces, AVI '10 - Rome, Italy
継続期間: 2010 5 262010 5 28

出版物シリーズ

名前Proceedings of the Workshop on Advanced Visual Interfaces AVI

Conference

ConferenceInternational Conference on Advanced Visual Interfaces, AVI '10
Italy
Rome
期間10/5/2610/5/28

ASJC Scopus subject areas

  • Software
  • Human-Computer Interaction

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  • これを引用

    Ji, W., Abe, Y., Ikenaga, T., & Goto, S. (2010). A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm. : Proceedings of the Working Conference on Advanced Visual Interfaces, AVI' 10 (pp. 207-212). (Proceedings of the Workshop on Advanced Visual Interfaces AVI). https://doi.org/10.1145/1842993.1843033