A partially-parallel decoder architecture for irregular LDPC code targeting high throughput and low cost applications is proposed. The design is based on a novel sum-delta message passing algorithm that facilitates the decoding throughput by removing redundant computations and decreases the hardware cost by optimizing the storage. Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.
|ホスト出版物のタイトル||Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|
|出版ステータス||Published - 2008|
|イベント||GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008 - Orlando, FL|
継続期間: 2008 3 4 → 2008 3 6
|Other||GLSVLSI 2008: 18th ACM Great Lakes Symposium on VLSI 2008|
|Period||08/3/4 → 08/3/6|
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