A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS

Cuilin Chen, Xiao Xu, Toshihiko Yoshimasu

研究成果: Conference contribution

2 引用 (Scopus)

抜粋

A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.

元の言語English
ホスト出版物のタイトル2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings
出版者Institute of Electrical and Electronics Engineers Inc.
ページ5-8
ページ数4
Part F134147
ISBN(電子版)9781538606407
DOI
出版物ステータスPublished - 2018 1 8
イベント2017 IEEE Asia Pacific Microwave Conference, APMC 2017 - Kuala Lumpur, Malaysia
継続期間: 2017 11 132017 11 16

Other

Other2017 IEEE Asia Pacific Microwave Conference, APMC 2017
Malaysia
Kuala Lumpur
期間17/11/1317/11/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Chen, C., Xu, X., & Yoshimasu, T. (2018). A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS. : 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings (巻 Part F134147, pp. 5-8). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APMC.2017.8251363