A delay variation and floorplan aware high-level synthesis algorithm with body biasing

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In this paper, we propose a delay variation and floorplan aware high-level synthesis algorithm with body biasing, which minimizes the average leakage energy of manufactured chips. To realize a floorplan-oriented high-level synthesis, we utilize a huddle-based distributed register architecture (HDR architecture), one of the DR architectures. HDR architecture divides the chip area into small partitions called a huddle and we can control a body bias voltage for every huddle. During high-level synthesis, we iteratively obtain expected leakage energy for every huddle when applying a body bias voltage. A huddle with smaller expected leakage energy contributes to reducing expected leakage energy of the entire circuit but can increase the latency. We assign CDFG nodes in critical paths to the huddles with larger expected leakage energy and those in non-critical paths to the huddles with smaller expected leakage energy. We expect to minimize the entire leakage energy in a manufactured chip without increasing its latency. Experimental results show that our algorithm reduces the average leakage energy by up to 38.9% without latency and yield degradation compared with typical-case design with body biasing.

本文言語English
ホスト出版物のタイトルProceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016
出版社IEEE Computer Society
ページ75-80
ページ数6
ISBN(電子版)9781509012138
DOI
出版ステータスPublished - 2016 5 25
イベント17th International Symposium on Quality Electronic Design, ISQED 2016 - Santa Clara, United States
継続期間: 2016 3 152016 3 16

出版物シリーズ

名前Proceedings - International Symposium on Quality Electronic Design, ISQED
2016-May
ISSN(印刷版)1948-3287
ISSN(電子版)1948-3295

Other

Other17th International Symposium on Quality Electronic Design, ISQED 2016
国/地域United States
CitySanta Clara
Period16/3/1516/3/16

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理

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