A depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured LUTs

Nozomu Togawa*, Koji Ara, Masao Yanagisawa, Tatsuo Ohtsuki

*この研究の対応する著者

研究成果: Article査読

1 被引用数 (Scopus)

抄録

This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound dc. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

本文言語English
ページ(範囲)473-481
ページ数9
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E82-A
3
出版ステータスPublished - 1999 1 1

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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