A Fast 8K x 8 Mixed CMOS Static RAM

Hirofumi Shinohara, Kenji Anami, Tsutomu Yoshihara, Yoshio Kohno, Yoichi Akasaka, Shinpei Kayano, Yuji Kihara

研究成果: Article査読

2 被引用数 (Scopus)

抄録

This paper describes a fast 8K x 8 static RAM fabricated with a mixed CMOS technology. To realize a fast access time and yet a low active power, a block-oriented die architecture with four submodules and a new sense amplifier are applied. An address access time of 34 ns and a chip select access time of 38 ns have been achieved at an active power of 90 mW. In addition to redundant memory cells, the RAM incorporates a spare element disable (SED) function to make it easy to obtain the information of the replaced memory cell. Another feature is a high latchup immunity of the CMOS peripheral circuits. This is obtained from an optimized well structure and guard baids around the wells. A 2-μm design rule combined with the double level polysilicon layer allowed for layout of the NMOS memory cell in 266.5 μm2and design of the die in 34.3 mm2.

本文言語English
ページ(範囲)1792-1796
ページ数5
ジャーナルIEEE Transactions on Electron Devices
32
9
DOI
出版ステータスPublished - 1985 9
外部発表はい

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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