A fast lock phase-locked loop using a continuous-time phase frequency detector

Jun Pan, Tsutomu Yoshihara

    研究成果: Conference contribution

    6 被引用数 (Scopus)

    抄録

    A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 μm technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.

    本文言語English
    ホスト出版物のタイトルIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
    ページ393-396
    ページ数4
    DOI
    出版ステータスPublished - 2007
    イベントIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 - Tainan
    継続期間: 2007 12 202007 12 22

    Other

    OtherIEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007
    CityTainan
    Period07/12/2007/12/22

    ASJC Scopus subject areas

    • 電子工学および電気工学
    • 電子材料、光学材料、および磁性材料

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