A fast selector-based subtract-multiplication unit and its application to butterfly unit

Youhei Tsukamoto, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

研究成果: Article

1 引用 (Scopus)

抜粋

Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit or a MAC unit which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtractmultiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. We apply them effectively to Radix- 2 butterfly units and Radix-4 butterfly units. Experimental results show that our proposed operation units using selector logics improves the performance by up to 13.92%, compared to a conventional approach.

元の言語English
ページ(範囲)60-69
ページ数10
ジャーナルIPSJ Transactions on System LSI Design Methodology
4
DOI
出版物ステータスPublished - 2011 12 5

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering

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