A fast selector-based subtract-multiplication unit and its application to Radix-2 butterfly unit

Youhei Tsukamoto*, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa

*この研究の対応する著者

研究成果: Conference contribution

抄録

Large-scale network and multimedia application LSIs include application specific arithmetic units. A multiply-accumulator unit (MAC unit) which is one of these optimized units arranges partial products and decreases carry propagations. However, there is no method similar to MAC to execute "subtract-multiplication". In this paper, we propose a high-speed subtract-multiplication unit that decreases latency of a subtract operation by bit-level transformation using selector logics. By using bit-level transformation, its partial products are calculated directly. The proposed subtract-multiplication units can be applied to even any types of systems using subtract-multiplications and a butterfly operation in FFT is one of their suitable applications. Experimental results show that our proposed arithmetic units using selector logics improves the performance by 13.92%, compared to a conventional approach.

本文言語English
ホスト出版物のタイトルProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
ページ1083-1086
ページ数4
DOI
出版ステータスPublished - 2010 12月 1
イベント2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
継続期間: 2010 12月 62010 12月 9

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
国/地域Malaysia
CityKuala Lumpur
Period10/12/610/12/9

ASJC Scopus subject areas

  • 電子工学および電気工学

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