A fine grain cooled logic architecture for low-power processors

Hiroyuki Matsubara, Takahiro Watanabe, Tadao Nakamura

研究成果: Conference article査読

抄録

In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.

本文言語English
ページ(範囲)735-740
ページ数6
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E84-A
3
出版ステータスPublished - 2001 3
外部発表はい
イベント13th Workshop on Circuits and Systems in Karuizawa - Karuizawa, Japan
継続期間: 2000 4 242000 4 25

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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