A fine-grain scalable and low memory cost variable block size motion estimation architecture for H.264/AVC

Zhenyu Liu*, Yang Song, Takeshi Ikenaga, Satoshi Goto

*この研究の対応する著者

研究成果: Article査読

21 被引用数 (Scopus)

抄録

One full search variable block size motion estimation (VBSME) architecture with integer pixel accuracy is proposed in this paper. This proposed architecture has following features: (1) Through widening data path from the search area memories, m processing element groups (PEG) could be scheduled to work in parallel and fully utilized, where m is a factor of sixteen. Each PEG has sixteen processing elements (PE) and just costs 8.5K gates. This feature provides users more flexibility to make tradeoff between the hardware cost and the performance. (2) Based on pipelining and multi-cycle data path techniques, this architecture can work at high clock frequency. (3) The memory partition number is greatly reduced. When sixteen PEGs are adopted, only two memory partitions are required for the search area data storage. Therefore, both the system hardware cost and power consumption can be saved. A 16-PEG design with 48 × 32 search range has been implemented with TSMC 0.18 μm CMOS technology. In typical work conditions, its maximum clock frequency is 261 MHz. Compared with the previous 2-D architecture [9], about 13.4 hardware cost and 5.7 power consumption can be saved.

本文言語English
ページ(範囲)1928-1936
ページ数9
ジャーナルIEICE Transactions on Electronics
E89-C
12
DOI
出版ステータスPublished - 2006 12月

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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