A Flexible Multiport RAM Compiler for Data Path

Hirofumi Shinohara, Kumiko Fujimori, Yoshiki Tsujihashi, Shuichi Kato, Yasutaka Horiba, Noriaki Matsumoto, Hiroomi Nakao, Akiharu Tada

研究成果: Article査読

18 被引用数 (Scopus)

抄録

A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. Wide bit-word organization range including 2048 words × 16 b and 512 words × 72 b was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to read and write ports, read/write ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no dc power consumption. The address access times of the generated three-port RAM's are, for example, 5.0 ns for 1K and 11.0 ns for 32K.

本文言語English
ページ(範囲)343-349
ページ数7
ジャーナルIEEE Journal of Solid-State Circuits
26
3
DOI
出版ステータスPublished - 1991 3月
外部発表はい

ASJC Scopus subject areas

  • 電子工学および電気工学

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