TY - GEN
T1 - A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs
AU - Fujiwara, Koichi
AU - Abe, Shinya
AU - Kawamura, Kazushi
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
PY - 2015/2/5
Y1 - 2015/2/5
N2 - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-aware HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distirbuted-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduces the number of slices by up to 47% and circuit delay by up to 16% compared with the conventional approach.
AB - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-aware HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distirbuted-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduces the number of slices by up to 47% and circuit delay by up to 16% compared with the conventional approach.
UR - http://www.scopus.com/inward/record.url?scp=84937855578&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84937855578&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2014.7032765
DO - 10.1109/APCCAS.2014.7032765
M3 - Conference contribution
AN - SCOPUS:84937855578
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 244
EP - 247
BT - 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Y2 - 17 November 2014 through 20 November 2014
ER -