A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Koichi Fujiwara, Shinya Abe, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-aware HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distirbuted-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduces the number of slices by up to 47% and circuit delay by up to 16% compared with the conventional approach.

本文言語English
ホスト出版物のタイトル2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ページ244-247
ページ数4
February
ISBN(電子版)9781479952304
DOI
出版ステータスPublished - 2015 2 5
イベント2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
継続期間: 2014 11 172014 11 20

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
番号February
2015-February

Other

Other2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
国/地域Japan
CityIshigaki Island, Okinawa
Period14/11/1714/11/20

ASJC Scopus subject areas

  • 電子工学および電気工学

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