A floorplan-aware high-level synthesis technique with delay-variation tolerance

Kazushi Kawamura, Yuta Hagio, Youhua Shi, Nozomu Togawa

    研究成果: Conference contribution

    2 引用 (Scopus)

    抜粋

    For realizing better trade-off between performance and yield rate in recent LSI designs, it is required to deal with increasing the ratios of interconnect delay as well as delay variation. In this paper, a novel floorplan-aware high-level synthesis technique with delay-variation tolerance is proposed. By utilizing floorplan-driven architectures, interconnect delays can be estimated and then handled even in high-level synthesis. Applying our technique enables to realize two scheduling/binding results (one is a non-delayed result and the other is a delayed result) simultaneously on a chip with small area/performance overhead, and either one of them can be selected according to the post-silicon delay variation. Experimental results demonstrate that our technique can reduce delayed scheduling/binding latency by up to 32.3% compared with conventional approaches.

    元の言語English
    ホスト出版物のタイトルProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
    出版者Institute of Electrical and Electronics Engineers Inc.
    ページ122-125
    ページ数4
    ISBN(印刷物)9781479983636
    DOI
    出版物ステータスPublished - 2015 9 30
    イベント11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore
    継続期間: 2015 6 12015 6 4

    Other

    Other11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
    Singapore
    Singapore
    期間15/6/115/6/4

      フィンガープリント

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    これを引用

    Kawamura, K., Hagio, Y., Shi, Y., & Togawa, N. (2015). A floorplan-aware high-level synthesis technique with delay-variation tolerance. : Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 122-125). [7285065] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285065