A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting FPGA designs

Koichi Fujiwara, Kazushi Kawamura, Shin Ya Abe, Masao Yanagisawa, Nozomu Togawa

    研究成果: Article

    2 引用 (Scopus)

    抄録

    Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same

    元の言語English
    ページ(範囲)1392-1405
    ページ数14
    ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
    E98A
    発行部数7
    DOI
    出版物ステータスPublished - 2015 7 1

    Fingerprint

    High-level Synthesis
    Field Programmable Gate Array
    Field programmable gate arrays (FPGA)
    Module
    Costs
    Slice
    Latency
    Scheduling
    Design
    High level synthesis
    Experimental Results
    Processing
    Demonstrate

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Computer Graphics and Computer-Aided Design
    • Applied Mathematics
    • Signal Processing

    これを引用

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    abstract = "Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47{\%} and latency by up to 22{\%} compared with conventional approaches while the number of required control steps is almost the same",
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    AU - Fujiwara, Koichi

    AU - Kawamura, Kazushi

    AU - Abe, Shin Ya

    AU - Yanagisawa, Masao

    AU - Togawa, Nozomu

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    AB - Recently, high-level synthesis (HLS) techniques for FPGA designs are required in various applications such as computerized stock tradings and reconfigurable network processings. In HLS for FPGA designs, we need to consider module floorplan and reduce multiplexer's cost concurrently. In this paper, we propose a floorplan-driven HLS algorithm for multiplexer reduction targeting FPGA designs. By utilizing distributed-register architectures called HDR, we can easily consider module floorplan in HLS. In order to reduce multiplexer's cost, we propose two novel binding methods called datapath-oriented scheduling/FU binding and datapath-oriented register binding. Experimental results demonstrate that our algorithm can realize FPGA designs which reduce the number of slices by up to 47% and latency by up to 22% compared with conventional approaches while the number of required control steps is almost the same

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    KW - FPGA

    KW - High-level synthesis (HLS)

    KW - Interconnection delay

    KW - MUX

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