A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration

    研究成果: Conference contribution

    1 被引用数 (Scopus)

    抄録

    As process technologies advance, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register (RDR) architecture has been proposed to cope with this problem. In this paper, we propose a floorplan-driven high-level synthesis algorithm using multiple-operation chainings composed of two or more operations, and reduce the overall latency targeting RDR architecture. Our algorithm enumerates multiple-operation-chaining path candidates before performing scheduling/binding. Based on them, we find out optimal ones taking into account RDR floorplan information. Experimental results show that our algorithm successfully reduces the latency by up to 30.4% compared to the conventional approaches.

    本文言語English
    ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
    出版社Institute of Electrical and Electronics Engineers Inc.
    ページ2129-2132
    ページ数4
    2015-July
    ISBN(印刷版)9781479983919
    DOI
    出版ステータスPublished - 2015 7 27
    イベントIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
    継続期間: 2015 5 242015 5 27

    Other

    OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
    国/地域Portugal
    CityLisbon
    Period15/5/2415/5/27

    ASJC Scopus subject areas

    • 電子工学および電気工学

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