A floorplan-driven high-level synthesis algorithm with operation chainings using chaining enumeration

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

In deep-submicron era, interconnection delays are not negligible even in high-level synthesis and RDR (Regular-Distributed-Register) architecture has been proposed to cope with this problem. In this paper, we propose a high-level synthesis algorithm using operation chainings which reduces the overall latency targeting RDR architectures. Our algorithm consists of three steps: The first step enumerates candidates for chaining. The second step introduces maximal chaining distance (MCD), which gives the maximum allowable distance on RDR architecture between chaining candidate operations. The last step performs list-scheduling and binding simultaneously using the results of two preceding steps. Our algorithm enumerates feasible chaining candidates and selects the best ones for RDR architecture. Experimental results show that our algorithm reduces the latency by up to 28.6%, the number of registers by up to 37.5%, the number of multiplexers by up to 25.0%, compared to the conventional approaches.

本文言語English
ホスト出版物のタイトル2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
出版社Institute of Electrical and Electronics Engineers Inc.
ページ248-251
ページ数4
February
ISBN(電子版)9781479952304
DOI
出版ステータスPublished - 2015 2 5
イベント2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014 - Ishigaki Island, Okinawa, Japan
継続期間: 2014 11 172014 11 20

出版物シリーズ

名前IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
番号February
2015-February

Other

Other2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
CountryJapan
CityIshigaki Island, Okinawa
Period14/11/1714/11/20

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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