TY - GEN
T1 - A FPGA-based dual-pixel processing pipelined hardware accelerator for feature point detection part in SIFT
AU - Jingbang, Q. I.U.
AU - Huang, Tianci
AU - Ikenaga, Takeshi
PY - 2009/12/1
Y1 - 2009/12/1
N2 - SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The feature point detection part, allocating final positions of all feature points, majorly defines the accuracy and stability of the whole system. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing dual-pixel processing and the 3-stage-interpolation pipelined architecture with use of dual-port DDR2 memory access, we achieve to further improve process speed, meanwhile keeping high accuracy. By experiment, our system proves to reach Max Clock Frequency of 145.0 MHz, processing up to 40 VGA images including memory operations. Compared with conventional work, hardware cost is slightly increased as trade-off for accelerated speed. High efficiency as 98.72% and high cover rate as 92.85% is kept by our proposal. Our proposal is suitable as a real-time SIFT system structure.
AB - SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The feature point detection part, allocating final positions of all feature points, majorly defines the accuracy and stability of the whole system. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing dual-pixel processing and the 3-stage-interpolation pipelined architecture with use of dual-port DDR2 memory access, we achieve to further improve process speed, meanwhile keeping high accuracy. By experiment, our system proves to reach Max Clock Frequency of 145.0 MHz, processing up to 40 VGA images including memory operations. Compared with conventional work, hardware cost is slightly increased as trade-off for accelerated speed. High efficiency as 98.72% and high cover rate as 92.85% is kept by our proposal. Our proposal is suitable as a real-time SIFT system structure.
KW - Dual-pixel processing
KW - FPGA
KW - Feature point detection
KW - Pipeline
KW - SIFT
UR - http://www.scopus.com/inward/record.url?scp=73549102207&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=73549102207&partnerID=8YFLogxK
U2 - 10.1109/NCM.2009.38
DO - 10.1109/NCM.2009.38
M3 - Conference contribution
AN - SCOPUS:73549102207
SN - 9780769537696
T3 - NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC
SP - 1668
EP - 1674
BT - NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC
T2 - NCM 2009 - 5th International Joint Conference on Int. Conf. on Networked Computing, Int. Conf. on Advanced Information Management and Service, and Int. Conf. on Digital Content, Multimedia Technology and its Applications
Y2 - 25 August 2009 through 27 August 2009
ER -