A FPGA-based dual-pixel processing pipelined hardware accelerator for feature point detection part in SIFT

Q. I.U. Jingbang, Tianci Huang, Takeshi Ikenaga

研究成果: Conference contribution

19 引用 (Scopus)

抜粋

SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The feature point detection part, allocating final positions of all feature points, majorly defines the accuracy and stability of the whole system. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing dual-pixel processing and the 3-stage-interpolation pipelined architecture with use of dual-port DDR2 memory access, we achieve to further improve process speed, meanwhile keeping high accuracy. By experiment, our system proves to reach Max Clock Frequency of 145.0 MHz, processing up to 40 VGA images including memory operations. Compared with conventional work, hardware cost is slightly increased as trade-off for accelerated speed. High efficiency as 98.72% and high cover rate as 92.85% is kept by our proposal. Our proposal is suitable as a real-time SIFT system structure.

元の言語English
ホスト出版物のタイトルNCM 2009 - 5th International Joint Conference on INC, IMS, and IDC
ページ1668-1674
ページ数7
DOI
出版物ステータスPublished - 2009 12 1
イベントNCM 2009 - 5th International Joint Conference on Int. Conf. on Networked Computing, Int. Conf. on Advanced Information Management and Service, and Int. Conf. on Digital Content, Multimedia Technology and its Applications - Seoul, Korea, Republic of
継続期間: 2009 8 252009 8 27

出版物シリーズ

名前NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC

Conference

ConferenceNCM 2009 - 5th International Joint Conference on Int. Conf. on Networked Computing, Int. Conf. on Advanced Information Management and Service, and Int. Conf. on Digital Content, Multimedia Technology and its Applications
Korea, Republic of
Seoul
期間09/8/2509/8/27

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications
  • Software

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  • これを引用

    Jingbang, Q. I. U., Huang, T., & Ikenaga, T. (2009). A FPGA-based dual-pixel processing pipelined hardware accelerator for feature point detection part in SIFT. : NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC (pp. 1668-1674). [5331581] (NCM 2009 - 5th International Joint Conference on INC, IMS, and IDC). https://doi.org/10.1109/NCM.2009.38