A FPGA-based real-time hardware accelerator for orientation calculation part in SIFT

Jingbang Qiu, Ying Lu, Tianci Huang, Takeshi Ikenaga

研究成果: Conference contribution

10 被引用数 (Scopus)

抄録

SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The Orientation Calculation Part, defining major orientation of feature points, enables selected image features to be invariant to rotation changes. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing LUT-Based Square Root Computation and Shifting-Based Orientation Calculation with use of dual-port DDR2 memory access, we achieve to reach real-time process speed, meanwhile keeping high accuracy. By experiment, our system proves to reach Max Clock Frequency of 130.0 MHz, processing up to around 256,000 feature points including memory operations. Compared with conventional work, hardware cost is remained at the same level. Accuracy is kept at 98.9% for over 40,000 feature points from 50 images. Our proposal is suitable for a real-time SIFT system.

本文言語English
ホスト出版物のタイトルIIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing
ページ1334-1337
ページ数4
DOI
出版ステータスPublished - 2009 12 1
イベントIIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing - Kyoto, Japan
継続期間: 2009 9 122009 9 14

出版物シリーズ

名前IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing

Conference

ConferenceIIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing
CountryJapan
CityKyoto
Period09/9/1209/9/14

ASJC Scopus subject areas

  • Computer Science(all)

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