A FPGA-based real-time hardware accelerator for orientation calculation part in SIFT

Jingbang Qiu, Ying Lu, Tianci Huang, Takeshi Ikenaga

研究成果: Conference contribution

8 引用 (Scopus)

抄録

SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The Orientation Calculation Part, defining major orientation of feature points, enables selected image features to be invariant to rotation changes. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing LUT-Based Square Root Computation and Shifting-Based Orientation Calculation with use of dual-port DDR2 memory access, we achieve to reach real-time process speed, meanwhile keeping high accuracy. By experiment, our system proves to reach Max Clock Frequency of 130.0 MHz, processing up to around 256,000 feature points including memory operations. Compared with conventional work, hardware cost is remained at the same level. Accuracy is kept at 98.9% for over 40,000 feature points from 50 images. Our proposal is suitable for a real-time SIFT system.

元の言語English
ホスト出版物のタイトルIIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing
ページ1334-1337
ページ数4
DOI
出版物ステータスPublished - 2009
イベントIIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing - Kyoto
継続期間: 2009 9 122009 9 14

Other

OtherIIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing
Kyoto
期間09/9/1209/9/14

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Particle accelerators
Field programmable gate arrays (FPGA)
Hardware
Data storage equipment
Real time systems
Computer hardware
Clocks
Processing
Costs
Experiments

ASJC Scopus subject areas

  • Computer Science(all)

これを引用

Qiu, J., Lu, Y., Huang, T., & Ikenaga, T. (2009). A FPGA-based real-time hardware accelerator for orientation calculation part in SIFT. : IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing (pp. 1334-1337). [5337207] https://doi.org/10.1109/IIH-MSP.2009.64

A FPGA-based real-time hardware accelerator for orientation calculation part in SIFT. / Qiu, Jingbang; Lu, Ying; Huang, Tianci; Ikenaga, Takeshi.

IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing. 2009. p. 1334-1337 5337207.

研究成果: Conference contribution

Qiu, J, Lu, Y, Huang, T & Ikenaga, T 2009, A FPGA-based real-time hardware accelerator for orientation calculation part in SIFT. : IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing., 5337207, pp. 1334-1337, IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing, Kyoto, 09/9/12. https://doi.org/10.1109/IIH-MSP.2009.64
Qiu J, Lu Y, Huang T, Ikenaga T. A FPGA-based real-time hardware accelerator for orientation calculation part in SIFT. : IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing. 2009. p. 1334-1337. 5337207 https://doi.org/10.1109/IIH-MSP.2009.64
Qiu, Jingbang ; Lu, Ying ; Huang, Tianci ; Ikenaga, Takeshi. / A FPGA-based real-time hardware accelerator for orientation calculation part in SIFT. IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing. 2009. pp. 1334-1337
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