A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi

Wenchao Zhang; Song Chen; Xuefei Bai; Dajiang Zhou

doi:10.1109/ASICON.2015.7517004

A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi

Wenchao Zhang, Song Chen, Xuefei Bai, Dajiang Zhou

研究成果: Conference contribution

4 引用（Scopus）

抜粋

This paper presents a full layer parallel quasi-cyclic low density parity check (QC-LDPC) code decoder for IEEE 802.16e (WiMAX) and IEEE 802.11n (Wi-Fi). By adopting three techniques including reusable fully parallel check node unit (CNU) structure, path rerouting network (PRN) and reusable permutation network (PN), the proposed decoder gets Gbps level throughput and could support two standards and most code modes of them with low hardware cost. By using turbo-decoding message-passing normalized min-sum (TDMP-NMS) decoding strategy, the bit error rate (BER) of the proposed decoder is decreasing fast to 10-5 at 2.2 dB. It only takes 30∼40/30∼60 clock cycles in each decoding iteration for WiMAX/Wi-Fi. Using SMIC 40nm low leakage HS RVT CMOS process and 7-bit quantization, the proposed decoder attains 789∼2227/470∼1879 Mbps for WiMAX/Wi-Fi at 290 MHz, 10 iterations, and only occupies 2.26 mm2 area.

元の言語	English
ホスト出版物のタイトル	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
出版者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781479984831
DOI	https://doi.org/10.1109/ASICON.2015.7517004
出版物ステータス	Published - 2016 7 19
イベント	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China 継続期間: 2015 11 3 → 2015 11 6

Other

Other	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
国	China
市	Chengdu
期間	15/11/3 → 15/11/6

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ASICON.2015.7517004

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これを引用

Zhang, W., Chen, S., Bai, X., & Zhou, D. (2016). A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi. ： Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 [7517004] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASICON.2015.7517004

Zhang, W, Chen, S, Bai, X & Zhou, D 2016, A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi. ： Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7517004, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7517004

@inproceedings{511e0a2e6a2d4c039fb0b774b6881761,

title = "A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi",

abstract = "This paper presents a full layer parallel quasi-cyclic low density parity check (QC-LDPC) code decoder for IEEE 802.16e (WiMAX) and IEEE 802.11n (Wi-Fi). By adopting three techniques including reusable fully parallel check node unit (CNU) structure, path rerouting network (PRN) and reusable permutation network (PN), the proposed decoder gets Gbps level throughput and could support two standards and most code modes of them with low hardware cost. By using turbo-decoding message-passing normalized min-sum (TDMP-NMS) decoding strategy, the bit error rate (BER) of the proposed decoder is decreasing fast to 10-5 at 2.2 dB. It only takes 30∼40/30∼60 clock cycles in each decoding iteration for WiMAX/Wi-Fi. Using SMIC 40nm low leakage HS RVT CMOS process and 7-bit quantization, the proposed decoder attains 789∼2227/470∼1879 Mbps for WiMAX/Wi-Fi at 290 MHz, 10 iterations, and only occupies 2.26 mm2 area.",

author = "Wenchao Zhang and Song Chen and Xuefei Bai and Dajiang Zhou",

year = "2016",

month = jul,

day = "19",

doi = "10.1109/ASICON.2015.7517004",

language = "English",

booktitle = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

note = "11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 ; Conference date: 03-11-2015 Through 06-11-2015",

}

TY - GEN

T1 - A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi

AU - Zhang, Wenchao

AU - Chen, Song

AU - Bai, Xuefei

AU - Zhou, Dajiang

PY - 2016/7/19

Y1 - 2016/7/19

N2 - This paper presents a full layer parallel quasi-cyclic low density parity check (QC-LDPC) code decoder for IEEE 802.16e (WiMAX) and IEEE 802.11n (Wi-Fi). By adopting three techniques including reusable fully parallel check node unit (CNU) structure, path rerouting network (PRN) and reusable permutation network (PN), the proposed decoder gets Gbps level throughput and could support two standards and most code modes of them with low hardware cost. By using turbo-decoding message-passing normalized min-sum (TDMP-NMS) decoding strategy, the bit error rate (BER) of the proposed decoder is decreasing fast to 10-5 at 2.2 dB. It only takes 30∼40/30∼60 clock cycles in each decoding iteration for WiMAX/Wi-Fi. Using SMIC 40nm low leakage HS RVT CMOS process and 7-bit quantization, the proposed decoder attains 789∼2227/470∼1879 Mbps for WiMAX/Wi-Fi at 290 MHz, 10 iterations, and only occupies 2.26 mm2 area.

AB - This paper presents a full layer parallel quasi-cyclic low density parity check (QC-LDPC) code decoder for IEEE 802.16e (WiMAX) and IEEE 802.11n (Wi-Fi). By adopting three techniques including reusable fully parallel check node unit (CNU) structure, path rerouting network (PRN) and reusable permutation network (PN), the proposed decoder gets Gbps level throughput and could support two standards and most code modes of them with low hardware cost. By using turbo-decoding message-passing normalized min-sum (TDMP-NMS) decoding strategy, the bit error rate (BER) of the proposed decoder is decreasing fast to 10-5 at 2.2 dB. It only takes 30∼40/30∼60 clock cycles in each decoding iteration for WiMAX/Wi-Fi. Using SMIC 40nm low leakage HS RVT CMOS process and 7-bit quantization, the proposed decoder attains 789∼2227/470∼1879 Mbps for WiMAX/Wi-Fi at 290 MHz, 10 iterations, and only occupies 2.26 mm2 area.

UR - http://www.scopus.com/inward/record.url?scp=84982279548&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84982279548&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2015.7517004

DO - 10.1109/ASICON.2015.7517004

M3 - Conference contribution

AN - SCOPUS:84982279548

BT - Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015

Y2 - 3 November 2015 through 6 November 2015

ER -