抄録
This paper presents a full layer parallel quasi-cyclic low density parity check (QC-LDPC) code decoder for IEEE 802.16e (WiMAX) and IEEE 802.11n (Wi-Fi). By adopting three techniques including reusable fully parallel check node unit (CNU) structure, path rerouting network (PRN) and reusable permutation network (PN), the proposed decoder gets Gbps level throughput and could support two standards and most code modes of them with low hardware cost. By using turbo-decoding message-passing normalized min-sum (TDMP-NMS) decoding strategy, the bit error rate (BER) of the proposed decoder is decreasing fast to 10-5 at 2.2 dB. It only takes 30∼40/30∼60 clock cycles in each decoding iteration for WiMAX/Wi-Fi. Using SMIC 40nm low leakage HS RVT CMOS process and 7-bit quantization, the proposed decoder attains 789∼2227/470∼1879 Mbps for WiMAX/Wi-Fi at 290 MHz, 10 iterations, and only occupies 2.26 mm2 area.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 |
出版社 | Institute of Electrical and Electronics Engineers Inc. |
ISBN(電子版) | 9781479984831 |
DOI | |
出版ステータス | Published - 2016 7 19 |
イベント | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China 継続期間: 2015 11 3 → 2015 11 6 |
Other
Other | 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 |
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Country | China |
City | Chengdu |
Period | 15/11/3 → 15/11/6 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering