A fully integrated PLL frequency synthesizer LSI for mobile communication system

T. Yasunaga, S. Hirano, M. Maeda, Y. Hiraoka, T. Andou, Y. Miyahara

研究成果: Paper査読

2 被引用数 (Scopus)

抄録

A fully integrated phase locked loop (PLL) frequency synthesizer LSI has been developed. This newly developed fractional-N type PLL LSI consists of an on-chip loop filter and a voltage controlled oscillator (VCO) with an on-chip resonator circuit. This VCO has a band-switching tuning circuit using MOS capacitors and an analog tuning circuit using PN varactor diodes. Both these tuning circuits are controlled automatically without external adjustment. The phase noise of the VCO at 2.2 GHz is -92.5 dBc/Hz at 50 kHz offset, while the frequency switching time is 170us.

本文言語English
ページ65-68
ページ数4
出版ステータスPublished - 2001
外部発表はい
イベント2001 IEEE Radio Frequency Integrated Circuits (RFIC) - Phoenix, AZ, United States
継続期間: 2001 5 202001 5 22

Conference

Conference2001 IEEE Radio Frequency Integrated Circuits (RFIC)
国/地域United States
CityPhoenix, AZ
Period01/5/2001/5/22

ASJC Scopus subject areas

  • 工学(全般)

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