A Fully Parallel 1-Mb CAM LSI for Real-Time Pixel-Parallel Image Processing

Takeshi Ikenaga, Takeshi Ogura

研究成果: Article査読

25 被引用数 (Scopus)

抄録

For real-time image-processing applications, a highly parallel system that exploits parallelism is desirable. A content addressable memory (CAM), or an associative processor, that can perform various types of parallel processing with words as the basic unit is a promising component for creating such a system because of its suitability for LSI implementation. Conventional CAM LSI's, however, have neither efficient function nor enough capacity for pixel-parallel processing. This paper describes a fully parallel 1-Mb CAM LSI. It has advanced functions for processing various pixel-parallel algorithms, such as mathematical morphology and discrete-time cellular neural networks. Moreover, since it has 16-K words, or processing elements (PE's), which can process 128 × 128 pixels in parallel, a board-sized pixel-parallel image-processing system can be implemented using several chips. A chip capable of operating at 56 MHz and 2.5 V was fabricated using 0.25-μm full-custom CMOS technology with five aluminum layers. A total of 15.5 million transistors have been integrated into a 16.1× 17.0 mm chip. Typical power dissipation is 0.25 W. Processing performance of various update and data transfer operations is 3-640 GOPS. This CAM LSI will make a significant contribution to the development of compact, high-performance image-processing systems.

本文言語English
ページ(範囲)536-543
ページ数8
ジャーナルIEEE Journal of Solid-State Circuits
35
4
DOI
出版ステータスPublished - 2000 4 1

ASJC Scopus subject areas

  • 電子工学および電気工学

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