A hard ware/S oft ware cosynthesis system for digital signal processor cores

研究成果: Article査読

16 被引用数 (Scopus)

抄録

This paper proposes a hardware/software cosynthesis system for digital signal processor cores and a hardware/software partitioning algorithm which is one of the key issues for the system. The target processor has a VLIW-type core which can be composed of a processor kernel multiple data memory buses (X-bus and Y-bus) hardware loop units addressing units and multiple functional units. The processor kernel includes five pipeline stages (RISC-type kernel) or three pipeline stages (DSP-type kernel). Given an application program written in the C language and a set of application data the system synthesizes a processor core by selecting an appropriate kernel (RISC-type or DSP-type kernel) and required hardware units according to the application program/data and the hardware costs. The system also generates the object code for the application program and a software environment (compiler and simulator) for the processor core. The experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program and the synthesized processor cores execute most application programs with the minimum number of clock cycles compared with several existing processors.

本文言語English
ページ(範囲)2325-2327
ページ数3
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E82-A
11
出版ステータスPublished - 1999 1 1

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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