A hardware accelerator with variable pixel representation & skip mode prediction for feature point detection part of SIFT algorithm

Jingbang Qiu, Tianci Huang, Yiqing Huang, Takeshi Ikenaga

研究成果: Conference contribution

5 引用 (Scopus)

抄録

Scale Invariant Feature Transform (SIFT) is well accepted as a robust feature point detection algorithm, which is invariant to rotation, scaling, illumination and viewpoint changes. Though powerful, high computation complexity acts as a bottleneck of the real-time systems. It is not until recently that the only hardware implementation scheme is proposed to reach real-time processing. In this paper, we propose a hardware accelerator structure of the Feature Point Detection part in SIFT which is possible to implement on FPGA. We apply integer-based Variable Pixel Representation which represents a pixel with variable number of registers in different computational stages to reduce redundant register consumption. Also, we introduce Skip Mode Prediction into the system, eliminating redundant computation, so as to shorten averaged computation time per pixel. Our work proves to speed up Max Clock Frequency for 75.0%, lower Register Consumption for 13.6%, and achieve higher Accuracy for 10-20% and Efficiency for 10.4% over conventional work. The proposal is more suitable for realtime system design of SIFT.

元の言語English
ホスト出版物のタイトルProceedings of the 11th IAPR Conference on Machine Vision Applications, MVA 2009
ページ239-242
ページ数4
出版物ステータスPublished - 2009
イベント11th IAPR Conference on Machine Vision Applications, MVA 2009 - Yokohama
継続期間: 2009 5 202009 5 22

Other

Other11th IAPR Conference on Machine Vision Applications, MVA 2009
Yokohama
期間09/5/2009/5/22

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Particle accelerators
Pixels
Mathematical transformations
Hardware
Real time systems
Field programmable gate arrays (FPGA)
Clocks
Lighting
Systems analysis
Processing

ASJC Scopus subject areas

  • Computer Vision and Pattern Recognition

これを引用

Qiu, J., Huang, T., Huang, Y., & Ikenaga, T. (2009). A hardware accelerator with variable pixel representation & skip mode prediction for feature point detection part of SIFT algorithm. : Proceedings of the 11th IAPR Conference on Machine Vision Applications, MVA 2009 (pp. 239-242)

A hardware accelerator with variable pixel representation & skip mode prediction for feature point detection part of SIFT algorithm. / Qiu, Jingbang; Huang, Tianci; Huang, Yiqing; Ikenaga, Takeshi.

Proceedings of the 11th IAPR Conference on Machine Vision Applications, MVA 2009. 2009. p. 239-242.

研究成果: Conference contribution

Qiu, J, Huang, T, Huang, Y & Ikenaga, T 2009, A hardware accelerator with variable pixel representation & skip mode prediction for feature point detection part of SIFT algorithm. : Proceedings of the 11th IAPR Conference on Machine Vision Applications, MVA 2009. pp. 239-242, 11th IAPR Conference on Machine Vision Applications, MVA 2009, Yokohama, 09/5/20.
Qiu J, Huang T, Huang Y, Ikenaga T. A hardware accelerator with variable pixel representation & skip mode prediction for feature point detection part of SIFT algorithm. : Proceedings of the 11th IAPR Conference on Machine Vision Applications, MVA 2009. 2009. p. 239-242
Qiu, Jingbang ; Huang, Tianci ; Huang, Yiqing ; Ikenaga, Takeshi. / A hardware accelerator with variable pixel representation & skip mode prediction for feature point detection part of SIFT algorithm. Proceedings of the 11th IAPR Conference on Machine Vision Applications, MVA 2009. 2009. pp. 239-242
@inproceedings{72123fe0c28242bf860275906409d999,
title = "A hardware accelerator with variable pixel representation & skip mode prediction for feature point detection part of SIFT algorithm",
abstract = "Scale Invariant Feature Transform (SIFT) is well accepted as a robust feature point detection algorithm, which is invariant to rotation, scaling, illumination and viewpoint changes. Though powerful, high computation complexity acts as a bottleneck of the real-time systems. It is not until recently that the only hardware implementation scheme is proposed to reach real-time processing. In this paper, we propose a hardware accelerator structure of the Feature Point Detection part in SIFT which is possible to implement on FPGA. We apply integer-based Variable Pixel Representation which represents a pixel with variable number of registers in different computational stages to reduce redundant register consumption. Also, we introduce Skip Mode Prediction into the system, eliminating redundant computation, so as to shorten averaged computation time per pixel. Our work proves to speed up Max Clock Frequency for 75.0{\%}, lower Register Consumption for 13.6{\%}, and achieve higher Accuracy for 10-20{\%} and Efficiency for 10.4{\%} over conventional work. The proposal is more suitable for realtime system design of SIFT.",
author = "Jingbang Qiu and Tianci Huang and Yiqing Huang and Takeshi Ikenaga",
year = "2009",
language = "English",
isbn = "9784901122092",
pages = "239--242",
booktitle = "Proceedings of the 11th IAPR Conference on Machine Vision Applications, MVA 2009",

}

TY - GEN

T1 - A hardware accelerator with variable pixel representation & skip mode prediction for feature point detection part of SIFT algorithm

AU - Qiu, Jingbang

AU - Huang, Tianci

AU - Huang, Yiqing

AU - Ikenaga, Takeshi

PY - 2009

Y1 - 2009

N2 - Scale Invariant Feature Transform (SIFT) is well accepted as a robust feature point detection algorithm, which is invariant to rotation, scaling, illumination and viewpoint changes. Though powerful, high computation complexity acts as a bottleneck of the real-time systems. It is not until recently that the only hardware implementation scheme is proposed to reach real-time processing. In this paper, we propose a hardware accelerator structure of the Feature Point Detection part in SIFT which is possible to implement on FPGA. We apply integer-based Variable Pixel Representation which represents a pixel with variable number of registers in different computational stages to reduce redundant register consumption. Also, we introduce Skip Mode Prediction into the system, eliminating redundant computation, so as to shorten averaged computation time per pixel. Our work proves to speed up Max Clock Frequency for 75.0%, lower Register Consumption for 13.6%, and achieve higher Accuracy for 10-20% and Efficiency for 10.4% over conventional work. The proposal is more suitable for realtime system design of SIFT.

AB - Scale Invariant Feature Transform (SIFT) is well accepted as a robust feature point detection algorithm, which is invariant to rotation, scaling, illumination and viewpoint changes. Though powerful, high computation complexity acts as a bottleneck of the real-time systems. It is not until recently that the only hardware implementation scheme is proposed to reach real-time processing. In this paper, we propose a hardware accelerator structure of the Feature Point Detection part in SIFT which is possible to implement on FPGA. We apply integer-based Variable Pixel Representation which represents a pixel with variable number of registers in different computational stages to reduce redundant register consumption. Also, we introduce Skip Mode Prediction into the system, eliminating redundant computation, so as to shorten averaged computation time per pixel. Our work proves to speed up Max Clock Frequency for 75.0%, lower Register Consumption for 13.6%, and achieve higher Accuracy for 10-20% and Efficiency for 10.4% over conventional work. The proposal is more suitable for realtime system design of SIFT.

UR - http://www.scopus.com/inward/record.url?scp=84872723928&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84872723928&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:84872723928

SN - 9784901122092

SP - 239

EP - 242

BT - Proceedings of the 11th IAPR Conference on Machine Vision Applications, MVA 2009

ER -