A hardware-efficient dual-standard VLSI architecture for MC interpolation in AVS and H.264

Zhou Dajiang*, Liu Peilin

*この研究の対応する著者

研究成果: Conference contribution

16 被引用数 (Scopus)

抄録

H.264 and AVS are the two latest video coding standards. Since the similarity between their structures, it is feasible to develop a dual-mode VLSI decoder for supporting both standards, with substantially less cost than the solution with two individual decoders. In this paper, we propose a dualstandard VLSI architecture for MC interpolation, which is the most calculation intensive module of the dual-mode decoder. By applying reconfigurable FIR filters and an adaptive pipeline strategy, an implementation of the architecture can process realtime video streams in 1280×720, 30fps at low cost (11.5k gates, no RAM). This design also provides scalability to meet higher performance requirements.

本文言語English
ホスト出版物のタイトルProceedings - IEEE International Symposium on Circuits and Systems
ページ2910-2913
ページ数4
出版ステータスPublished - 2007
外部発表はい
イベント2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
継続期間: 2007 5月 272007 5月 30

Other

Other2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007
国/地域United States
CityNew Orleans, LA
Period07/5/2707/5/30

ASJC Scopus subject areas

  • 電子材料、光学材料、および磁性材料
  • 電子工学および電気工学

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