A hardware/software cosynthesis system for digital signal processor cores with two types of register files

研究成果: Article査読

9 被引用数 (Scopus)

抄録

In digital signal processing, bit width of intermediate variables should be longer than that of input and output variables in order to execute intermediate operations with high precision. Then a processor core for digital signal processing is required to have two types of register files, one of which is used by input and output variables and the other one is used by intermediate variables. This paper proposes a hardware/software cosynthesis system for digital signal processor cores with two types of register files. Given an application program and its data, the system synthesizes a hardware description of a processor core, an object code running on the processor core, and software environments. A synthesized processor core can be composed of a processor kernel, multiple data memory buses, hardware loop units, addressing units, and multiple functional units. Furthermore it can have two types of register files RFi and RF-z. The bit width and number of registers in RFi or RF% will be determined based on a given application program. Thus a synthesized processor core will have small area with keeping high precision of intermediate operations compared with a processor core with only one register file. The experimental results demonstrate the effectiveness of the proposed system.

本文言語English
ページ(範囲)442-451
ページ数10
ジャーナルIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E83-A
3
出版ステータスPublished - 2000 1 1

ASJC Scopus subject areas

  • 信号処理
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • 電子工学および電気工学
  • 応用数学

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