A hardware/software partitioning algorithm for digital signal processor cores with two types of register files

Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki

研究成果: Paper

1 引用 (Scopus)

抜粋

This paper proposes a hardware/software partitioning algorithm for digital signal processor cores with two register files. Given a compiled assembly code and a timing constraint of execution time, the proposed algorithm generates a processor core configuration with a new assembly code running on the generated processor core. The proposed algorithm considers two register files and determines the number of registers in each of register files. Moreover the algorithm considers two or more functional units for each arithmetic or logical operation and assigns functional units with small area to a processor core without causing performance penalty. A generated processor core will have small area compared with processor cores which have a single register file or those which have only one functional unit for each operation. The experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.

元の言語English
ページ544-547
ページ数4
出版物ステータスPublished - 2000 12 1
イベント2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, China
継続期間: 2000 12 42000 12 6

Conference

Conference2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems
China
Tianjin
期間00/12/400/12/6

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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  • これを引用

    Togawa, N., Sakurai, T., Yanagisawa, M., & Ohtsuki, T. (2000). A hardware/software partitioning algorithm for digital signal processor cores with two types of register files. 544-547. 論文発表場所 2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems, Tianjin, China.